This invention relates in general to digital timing circuits, and more particularly to a digital phase locked loop capable of recovering a clock signal from one or more inputs signals subject to jitter.
In digital networking applications, there is a requirement to provide timing reference for the SONET (synchronous optical network) OC-N and STS-N interface circuits, and T1 or E1 primary rate digital transmission links. These timing signals must meet relevant standards such as BELLCORE GR-1244-CORE and GR-253-CORE recommendations for STRATUM 3E3 and 4E clocks and SONET Minimum Clock (SMC). These specifications impose strict requirements on jitter and stability.
The common method of providing such timing signals is to use a phase locked loop (PLL). Typically, a PLL consists of a phase detector that compares the input signal with the output of the loop divided by a suitable factor; a loop filter to eliminate high frequency fluctuations; and a controlled oscillator whose frequency is controlled in such a way as to eliminate the phase difference detected by the phase detector.
It has long been known to employ a VCO (voltage controlled oscillator) as the controlled oscillator in the loop. U.S. Pat. No. 4,577,163 discloses a phase lock loop in which the VCO is replaced by a DCO (digital controlled oscillator) whose output is divided by factor K and fed back to the phase detector. In the ""163 patent, the DCO is clocked by a clock signal Fclk. Since the DCO cannot respond to a phase shift less than one clock cycle, Fclk is the limiting factor for accuracy in this type of phase locked loop. In order to meet BELLCORE and SMC specifications, a local oscillator having a frequency of 5 GHz or more must be employed. Such a high frequency local oscillator is expensive, energy consuming, and prone to the emission of electromagnetic interference (EMI).
U.S. Pat. No. 5,218,314 discloses a phase locked loop in which a local oscillator feeds a tapped delay line. The output signal is taken from one of the taps of the delay line according to a phase comparison effected with the input signal. The problem with this arrangement is that it provides no jitter suppression for the reference signals. As a practical matter, due to the inherent properties of the transmission medium, incoming signals will be subject to jitter, and this must be substantially suppressed in order to meet the BELLCORE specifications.
U.S. Pat. No. 5,602,884, the contents of which are incorporated herein by reference, discloses a phased locked loop using a combination of a DCO clocked by a 20 MHz clock and a tapped delay line. Since the DCO directly controls the tapped delay line, jitter free precision can be maintained to a fraction of a clock cycle. The fraction is limited by the delay time of each tap of the tapped delay line. Using a tapped delay line with 64 taps, a typical unfiltered intrinsic output jitter is 0.04 UI (Unit Interval) peak-to-peak. In order to meet SMC specifications, a tapped delay line with 1024 taps would have to be employed.
The conventional approach in using a tapped delay line is using fixed delay taps, where a chain of either similar buffers or similar inverters, having the same delay time, are connected in series. A 20 MHz local oscillator reference clock (50 nsec) can not easily be divided in 50 psec or smaller delay steps due to both the size of the hardware and the power consumption. A 50 psec delay step fits 1000 times in 50 nsec. For example, the 64 taps in a Multitrunk System Synchronizer available from Mitel Corporation under the product number MT9042 requires about 2k gates. Using the same solution for a 50 psec delay step would require roughly 150k gates, with a power consumption of between 400 mA to 900 mA.
The fundamental disadvantage of the tapped delay line with fixed delay tap is that the delay resolution can only be increased with a linear increase in the number of taps and therefore the number of gates required and power consumption.
An object of the invention is to provide a phase locked loop that alleviates the aforementioned problems with the prior art.
According to a first aspect of the present invention there is provided a digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter, comprising:
a) a digital input circuit receiving the at least one input signal;
b) a digital controlled oscillator for generating an output at a desired frequency and a control signal representing the time error in the output signal;
c) a stable local oscillator for providing clock signals to the digital controlled oscillator;
d) a plurality of tapped delay lines, the tapped delay lines comprising a plurality of delay means, the sum of the delay of the plurality of tapped delay lines being less than one clock cycle of the digital controlled oscillator; the plurality of tapped delay lines including a coarse, tapped delay line for receiving the output signal of the digital controlled oscillator; and a fine, tapped delay line for receiving the output signal of the coarse tapped delay line, the fine tapped delay line comprising a plurality of delay means proportional to one of the coarse tapped delay line; and
a digital phase comparator for receiving the at least one input signal from the input circuit and the output signal from the second tapped delay line means to generate a digital input signal controlling the digital controlled oscillator,
wherein the digital controlled oscillator is an adding type rate multiplier that generates the output signal when attaining an overflow condition, the remainder term upon attainment of the overflow condition generating the control signal.
According to a second aspect of the present invention there is provided a method of recovering a stable clock signal from at least two input signals subject to jitter, comprising the steps of:
generating local clock signals with a stable oscillator;
clocking a digital controlled oscillator with the local clock signals;
feeding a first output of the digital controlled oscillator to a first tapped delay line;
feeding an output of the first tapped delay line to a second tapped delay line; wherein the second tapped delay line has a proportional relationship to the first tapped delay line;
controlling the first and second tapped delay lines with a second output of the digital controlled oscillator representative of a timing error in the first output to generate clock signals having a precision greater than one clock cycle of the stable oscillator;
controlling the digital controlled oscillator with a digital phase comparator that compares the output thereof with the at least one input signal; and
wherein a virtual reference signal is created that has a constant phase relationship to the at least two input signals such that any phase jump occurring on changeover between the input signals is minimized.